Many semiconductors can be used for acquiring a signal indicative of an image. Charge coupled devices (CCDs), photodiode arrays, charge injection devices and hybrid focal plane arrays are some of the more commonly used devices. CCDs are often used, since they represent a mature technology, are capable of large formats and very small pixel size and they facilitate noise-reduced charge domain processing techniques such as binning and time delay integration.
However, CCD imagers suffer from a number of drawbacks. For example, the signal fidelity of a CCD decreases as the charge transfer efficiency is raised to the power of the number of stages. Since CCDs use many stages, the CCD fabrication technique needs to be optimized for very efficient charge transfer efficiency. CCDs are also susceptible to radiation damage, require good light shielding to avoid smear and have high power dissipation for large arrays.
The specialized CCD semiconductor fabrication process is intended to maximize the charge transfer efficiency of the CCD. This specialized CCD process, however, has been incompatible with the complementary metal oxide semiconductor (“CMOS”) processing which has been conventionally used. The image signal processing electronics required for the imager are often fabricated in CMOS. Accordingly, it has been difficult to integrate on-chip signal processing electronics in a CCD imager, because of the incompatibility of the processing techniques. Because of this problem, the signal processing electronics has often been carried out off-chip.
Typically, each column of CCD pixels is transferred to a corresponding cell of a serial output register, whose output is amplified by a single on-chip amplifier (e.g., a source follower transistor) before being processed in off-chip signal processing electronics. This architecture limits the read-out frame rate which the on-chip amplifier can handle proportional to the number of charge packets divided by the number of pixels in the imager.
The other types of imager devices have problems as well. Photodiode arrays exhibit high kTC noise. This makes it impractical to reset a diode or capacitor node to the same initial voltage at the beginning of each integration period. Photodiode arrays also suffer from lag. Charge injection devices also have high noise.
Hybrid focal plane arrays exhibit less noise but are prohibitively expensive for many applications and have relatively small array sizes.
In view of the inventor's recognition of the above problems, it is one object of the present invention to provide an imager device which has the low kTC noise level of a CCD without the associated CMOS incompatibility and other above-described problems.
In a preferred embodiment, the sensing node of the charge coupled device section includes a floating diffusion, and the charge coupled device stage includes a transfer gate overlying the substrate between the floating diffusion and the photogate. This preferred embodiment can further include apparatus for periodically resetting a potential of the sensing node to a predetermined potential, including a drain diffusion connected to a drain bias voltage and a reset gate between the floating diffusion and the drain diffusion, the reset gate connected to a reset control signal.
The imaging device also includes a readout circuit having at least an output transistor. Preferably, the output transistor is a field effect source follower output transistor formed in each one of the pixel cells, the floating diffusion being connected to its gate. Also, the readout circuit can further include a field effect load transistor connected to the source follower output transistor, and preferably a correlated double sampling circuit having an input node connected between the source follower output transistor and load transistor. The focal array of cells is also preferably organized by rows and columns, and the readout circuit has plural load transistors and plural correlated double sampling circuits. In this case, each cell in each column of cells is connected to a single common load transistor and a single common correlated double sampling circuit. These common load transistors and correlated double sampling circuits are disposed at the bottom of the respective columns of cells to which they are connected.
In the preferred implementation, charge is first accumulated under the photogate of a pixel cell. Next, the correlated double sampling circuit samples the floating diffusion immediately after it has been reset, at one capacitor. The accumulated charge is then transferred to the floating diffusion and the sampling process is repeated with the result stored at another capacitor. The difference between the two capacitors is the signal output. In accordance with a further refinement, this difference is corrected for fixed pattern noise by subtracting from it another difference sensed between the two capacitors while they are temporarily shorted.
The imaging device can also have a micro-lens layer overlying the substrate. This micro-lens layer includes a refractive layer and individual lenses formed in the layer which are in registration with individual ones of the cells. Each of the individual lenses has a curvature for focusing light toward a photosensitive portion of the respective cell.
The imaging device could also use a Simple Floating Gate (“SFG”) pixel structure. This SFG pixel allows non-destructive readout due to the floating gate configuration. As described herein, the device made using the SFG has fewer components. Therefore, the system allows the use of smaller pixel sizes. The SFG pixel structure described herein forms to construct high density arrays that allow a non-destructive readout. An array of SFG pixels includes a monolithic semiconductor integrated circuit substrate and is organized by rows and columns, as with previously-described imager embodiments. However, each SFG pixel cell includes a photogate overlying the substrate which operates to accumulate photo-generated charge thereunder. A coupling capacitor is connected between the photogate and a row address line. The row address line is common to all the pixel cells in a row of the array, a barrier gate overlies the substrate adjacent to the photogate. The barrier gate is connected to a barrier gate bias voltage. In addition, a readout circuit including an output transistor is preferably formed in each one of the cells. This output transistor has a source and drain diffusion formed in said substrate and a gate overlying said substrate between said source and drain diffusions. The drain diffusion is connected to a drain bias voltage, the output transistor gate is connected to the photogate, and the source diffusion is connected to a column signal line which is common to all the pixel cells in a column of the array. Preferably, a load transistor is also connected to the output transistor, as well as a noise suppression circuit. The load transistor and noise suppression circuit are preferably connected to the output transistor via the column signal line, thereby creating a common load transistor and noise suppression circuit for every pixel cell in the column of the array. Therefore, each column of the array would have a separate load transistor and noise suppression circuit. In addition, the load transistors and noise suppression circuits are disposed at the bottom of the respective columns of cells connected thereto. The noise suppression circuit is preferably the same as the previously-described correlated double sampling circuit.
The SFG pixel operates in an integrating mode by biasing the photogate to a voltage greater than the barrier gate bias voltage. This allows charge to accumulate in the portion of the substrate underlying the photogate. Also, the drain bias voltage exceeds the photogate bias voltage and the barrier gate bias voltage is set so as to prevent blooming by causing charge in excess of a prescribed amount to drain to a potential well created under the drain diffusion of the output transistor by the drain bias voltage. The pixel is readout by increasing the photogate bias voltage to a level exceeding other pixels not being readout. In order to facilitate the noise suppression process, the readout process is preferably done twice, once after charge has been accumulated in the integration period, and once after the pixel has been reset. The pixel is reset by lowering the photogate bias voltage to a level below that of the barrier gate bias voltage. Since the barrier gate voltage is lower than the drain bias voltage, the accumulated charge drains from the portion of the substrate underlying the photogate to the potential well created under the drain diffusion of the output transistor by the drain bias voltage.
It is also noted that an array of SFG pixels preferably includes the micro-lens layer overlying said substrate. The microlens layer is employed to focus light toward a photosensitive portions of the cells.
In addition to the just described benefits, other objectives and advantages of the present invention will become apparent from the detailed description which follows hereinafter when taken in conjunction with the drawing accompanying figures.